Create a table showing the forwarding logic for the R4000 integer pipeline using the same format as
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Figure C.26
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Pipeline register containing destination Opcode of destination forwarded instruction Destination Pipeline register containing source instruction Opcode of source of the Comparison (if equal then forward) instruction result instruction Register- register ALU Register-register ALU, ALU immediate, load, store, branch EX/MEM.IR[rd] ID/EX.IR[rs] EX/MEM ID/EX Top ALU input EX/MEM.IR[rd] == ID/EX.IR[rt] EX/MEM Register- register ALU ID/EX Register-register ALU Bottom ALU input MEM/WB.IR[rd] == ID/EX.IR[rs] MEM/WB Register- register ALU ID/EX Register-register ALU, ALU immediate, load, Top ALU input store, branch Bottom ALU MEM/WB.IR[rd] ID/EX.IR[rt] EX/MEM.IR[rt] == ID/EX.IR[rs] MEM/WB Register- register ALU ID/EX Register-register ALU == input EX/MEM ALU ID/EX Register-register ALU, ALU immediate, load, Top ALU input %3%3D immediate store, branch EX/MEM.IR[rt] == ID/EX.IR[rt] Register-register ALU EX/MEM ALU ID/EX Bottom ALU immediate input Top ALU input ALU ID/EX Register-register ALU, ALU immediate, load, store, branch MEM/WB.IR[rt] == ID/EX.IR[rs] MEM/WB %3%3D immediate Register-register ALU Bottom ALU MEM/WB.IR[rt] ID/EX.IR[rt] MEM/WB ALU ID/EX immediate input Register-register ALU, Top ALU ALU immediate, load, input MEM/WB MEM/WB.IR[rt] == ID/EX.IR[rs] Load ID/EX store, branch Register-register ALU MEM/WB.IR[rt] : ID/EX.IR[rt] MEM/WB Load ID/EX Bottom ALU input
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Related Book For
Computer Architecture A Quantitative Approach
ISBN: 978-8178672663
5th edition
Authors: John L. Hennessy, David A. Patterson
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