This problem evaluates the cache performances for different loop orderings. You are asked to consider the...
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This problem evaluates the cache performances for different loop orderings. You are asked to consider the following two loops, written in C, which calculate the sum of the entries in a 128 by 64 matrix of 32-bit integers: Loop B sum = 0; for (j=0; j<64; j++) for (i = 0; i < 128; i++) sum += A[i][i]: Loop A sum = 0; for (i =0; i<128; i++) for(j 0; j<64; j++) sum + Aillil: The matrix A is stored contiguously in memory in row-major order. Row major order means that elements in the same row of the matrix are adjacent in memory as shown in the following memory layout: A[i][j] resides in memory location [4*(64*i+j)] Memory Location: 0 A[0][0] | A[0][1] 252 A[0][63] 256 A[1][O]... 4 (64 127+63) A[127][63] (a) Consider a 4KB direct-mapped data cache with 32-byte (8-word) cache blocks. Calculate the number of cache misses that will occur when running Loop A. Calculate the number of cache misses that will occur when running Loop B. Assume that the caches are initially empty. Show all your work to get full credit. (b) Consider a direct-mapped data cache with 32-byte 8 (8-word) cache blocks. Calculate the minimum number of cache blocks required for the data cache if Loop A is to run without any cache misses other than compulsory misses. Calculate the minimum number of cache blocks required for the data cache if Loop B is to run without any cache misses other than compulsory misses. Explain your reasoning. This problem evaluates the cache performances for different loop orderings. You are asked to consider the following two loops, written in C, which calculate the sum of the entries in a 128 by 64 matrix of 32-bit integers: Loop B sum = 0; for (j=0; j<64; j++) for (i = 0; i < 128; i++) sum += A[i][i]: Loop A sum = 0; for (i =0; i<128; i++) for(j 0; j<64; j++) sum + Aillil: The matrix A is stored contiguously in memory in row-major order. Row major order means that elements in the same row of the matrix are adjacent in memory as shown in the following memory layout: A[i][j] resides in memory location [4*(64*i+j)] Memory Location: 0 A[0][0] | A[0][1] 252 A[0][63] 256 A[1][O]... 4 (64 127+63) A[127][63] (a) Consider a 4KB direct-mapped data cache with 32-byte (8-word) cache blocks. Calculate the number of cache misses that will occur when running Loop A. Calculate the number of cache misses that will occur when running Loop B. Assume that the caches are initially empty. Show all your work to get full credit. (b) Consider a direct-mapped data cache with 32-byte 8 (8-word) cache blocks. Calculate the minimum number of cache blocks required for the data cache if Loop A is to run without any cache misses other than compulsory misses. Calculate the minimum number of cache blocks required for the data cache if Loop B is to run without any cache misses other than compulsory misses. Explain your reasoning.
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Consider the given question Two loops written in C language are given The answer and explanation for the answer are provided in the next steps Explana... View the full answer
Related Book For
Computer Architecture A Quantitative Approach
ISBN: 978-0123704900
4th edition
Authors: John L. Hennessy, David A. Patterson
Posted Date:
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