(a) Design the saturated load inverter circuit in Figure 16.5 (a) such that the power dissipation is \(0.30 \mathrm{~mW}\) and the output voltage is \(0.08 \mathrm{~V}\) for \(v_{I}=1.4 \mathrm{~V}\). The circuit is biased at \(V_{D D}=1.8 \mathrm{~V}\) and the transistor threshold voltage of each transistor is \(V_{T N O}=0.4 \mathrm{~V}\).

(b) Using the results of part (a), find the range of input voltage such that the driver transistor is biased in the saturation region.

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VDD iDL ip + Load: VDSL VTNL, KL + VGSL iDD + UDSD Driver: VIND, KD + VGSD (a) = - VDS (sat) VGS VTN Transition point VDD-VTNL VDD "DS (b) Figure 16.5 (a) NMOS inverter with saturated load and (b) driver transistor characteristics and load curve