A low-power TTL logic gate with an active pnp pull-up device is shown in Figure P17.35. The

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A low-power TTL logic gate with an active pnp pull-up device is shown in Figure P17.35. The transistor parameters are $\beta_{F}=100$ and $\beta_{R}=0.2$ (for each input emitter). Assume a fanout of 5.

(a) For $v_{X}=v_{Y}=v_{Z}=0.1 \mathrm{~V}$, determine $i_{B 1}, i_{B 2}, i_{B 3}, i_{C 2}$, and $i_{C 3}$.

(b) Repeat part (a) for $v_{X}=v_{Y}=$ $v_{Z}=2 \mathrm{~V}$.

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Microelectronics Circuit Analysis And Design

ISBN: 9780071289474

4th Edition

Authors: Donald A. Neamen

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Question Posted: May 09, 2024 01:02 PM

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A low-power TTL logic gate with an active pnp pull-up device is shown in Figure P17.35. The

Question:

RB1 1 iB1. RB2= 1 www iB3 +2 V Q3 Vo vxo- Q2 Vy o 182 Figure P17.35

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Microelectronics Circuit Analysis And Design

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