The circuit configuration shown in Figure P17.21 is redesigned such that \(V_{C C}=3.3 \mathrm{~V}, R_{1}=16 \mathrm{k} \Omega, R_{C}=6 \mathrm{k} \Omega\), and \(R_{B}=20 \mathrm{k} \Omega\). Let \(\beta=50\).

(a) Determine \(i_{1}, i_{3}, i_{4}\), and \(v^{\prime}\) for (i) \(v_{X}=0.1 \mathrm{~V}, v_{Y}=3.3 \mathrm{~V}\) and (ii) \(v_{X}=v_{Y}=3.3 \mathrm{~V}\).

(b) Calculate the maximum fanout for the output low condition such that \(Q_{1}\) remains biased in saturation.

(c) Repeat part (b) if the maximum collector current is limited to \(5 \mathrm{~mA}\).

Transcribed Image Text:

Dx Uyo K Vcc=5 V R = 8kQ D1 D2 RC= 2.4 KK Rg 15 k Dy Figure P17.21