The transistor parameters for the circuit in Figure P16.21 are: \(V_{T N}=0.8 \mathrm{~V}\) for all enhancement-mode devices, \(V_{T N}=-2 \mathrm{~V}\) for the depletion-mode devices, and \(k_{n}^{\prime}=60 \mu \mathrm{A} / \mathrm{V}^{2}\) for all devices. The width-to-length ratios of \(M_{L 2}\) and \(M_{L 3}\) are 1 , and those for \(M_{D 2}, M_{D 3}\), and \(M_{D 4}\) are 8.

(a) For \(v_{X}=5 \mathrm{~V}\), output \(v_{O 1}\) is \(0.15 \mathrm{~V}\), and the power dissipation in this inverter is to be no more than \(250 \mu \mathrm{W}\). Determine ( \(W / L)_{M L 1}\) and ( \(\left.W / L\right)_{M D 1}\).

(b) For \(v_{X}=v_{Y}=0\), determine \(v_{O 2}\).

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5 V 5 V 5 V MLI M2 102 M13 1036 3011 y o Mp Mm2 Mp3 oly Figure P16.21