For flip-flop C of Table 15.1 and a 2 GHz clock, check Figure 15.19 for timing violations.
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For flip-flop C of Table 15.1 and a 2 GHz clock, check Figure 15.19 for timing violations. If there is a hold violation, indicate where delay must be added, the necessary delay, specify and recheck for setup violations. If there is a setup violation, calculate the maximum error-free frequency.
Data in Figure 15.19
Transcribed Image Text:
Logic A t₁ = 10 ps ta= 400 ps Logic B t₁ = 100 ps td = 200 ps Logic C tc =30 ps td = 50 ps X Y Z
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Based on the given information we can assume that flipflop C has a setup time ts of 30 ps and a hold time th of 50 ps The clock frequency is 2 GHz which means the clock period T is 05 ns To check for ...View the full answer
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Related Book For
Digital Design Using VHDL A Systems Approach
ISBN: 9781107098862
1st Edition
Authors: William J. Dally, R. Curtis Harting, Tor M. Aamodt
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