Indicate the final decimal value of the regA and regB after executing the following instructions. reg[8:0] regA;

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Indicate the final decimal value of the regA and regB after executing the following instructions.
reg[8:0] regA;
reg[8:0] regB;
regA <= $unsigned -9;
regB <= $signed 9'b100000000;

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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