(a) A bias-stable circuit with the configuration shown in Figure P5.61 is to be designed such that \(I_{C Q}=(3 \pm 0.1) \mathrm{mA}\) and \(V_{C E Q} \cong 5 \mathrm{~V}\) using a transistor with \(75 \leq \beta \leq 150\).

(b) Sketch the load line and plot the range of \(Q\)-point values for part (a).

Transcribed Image Text:

+ Cc ww V+=+6 V ww R Rc=2kQ Figure P5.61 V-=-6 V RE=200 2