Assume the cache contents of Figure 4.37 and the timing of Implementation 1 in Figure 4.38. What

Question:

Assume the cache contents of Figure 4.37 and the timing of Implementation 1 in Figure 4.38. What are the total stall cycles for the following code sequences with both the base protocol and the new MESI protocol in Exercise 4.5? Assume state transitions that do not require bus transactions incur no additional stall cycles.
a. P0: read 100 P0: write 100 <-- 40
b. P0: read 120 P0: write 120 <-- 60
c. P0: read 100 P0: read 120
d. P0: read 100 P1: write 100 <-- 60
e. P0: read 100 P0: write 100 <-- 60
P1: write 100 <-- 40