Figure 14.14 shows an example of a superscalar processor organization. The processor can issue two instructions per cycle if there is no resource conflict and no data dependence problem. There are essentially two pipelines, with four processing stages (fetch, decode, execute, and store). Each pipeline has its own fetch decode and store unit. Four functional units (multiplier, adder, logic unit, and load unit) are available for use in the execute stage and are shared by the two pipelines on a dynamic basis. The two store units can be dynamically used by the two pipelines, depending on availability at a particular cycle. There is a look ahead window with its own fetch and decoding logic. This window is used for instruction look ahead for out-of-order instruction issue.
Consider the following program to be executed on this processor:

a. What dependencies exist in the program?
b. Show the pipeline activity for this program on the processor of Figure 14.14 using in-order issue with in-order completion policies and using a presentation similar to Figure 14.2.

Figure 14.14 A Dual-Pipeline Superscalar Processor
c. Repeat for in-order issue with out-of-order completion.
d. Repeat for out-of-order issue with out-of-order completion.

I1: Load R1, A I2: Add R2, R1 I3 Add R3, R4 I4: Mul R4, R5 I5: Comp R6 I6: Mul R6, R7 /R1 Memory (A) / /R2 (R2) + R(1)/ /R3(R3R (4)/ /R4 (R4 ) + R(5)/ /R3 (R3) + R(4)/ Fetch Decode stage Store i (write! back) Execute stage Multiplier ml m2 m3 Adder stage fl d1 sl al f2 d2 Logic f3 d3 Load Lookahead window