Exercise 4.3 Problems in this exercise refer to the following logic block:

Logic Block

a. Small I-Memory with four 8-bit words

b. Small Registers unit with two 8-bit registers 4.3.1 [5] <4.1, 4.2> Does this block contain logic only, fl ip-fl ops only, or both?

4.3.2 [20] <4.1, 4.2> Show how this block can be implemented. Use only AND, OR, NOT, and D-elements.

4.3.3 [10] <4.1, 4.2> Repeat Exercise 4.3.2, but the AND and OR gates you use must all be 2-input gates.

Cost and latency of digital logic depends on the kinds of basic logic elements

(gates) that are available and on the properties of these gates. The remaining three problems in this exercise refer to these gates, latencies, and costs:

NOT 2-input AND or OR Each additional input for AND/OR D-element Latency Cost Latency Cost Latency Cost Latency Cost

a. 20ps 1 30ps 2 +0ps +1 40ps 6

b. 50ps 1 100ps 2 +40ps +1 160ps 2 4.3.4 [5] <4.1, 4.2> What is the latency of your implementation from Exercise 4.3.2?
4.3.5 [5] <4.1, 4.2> What is the cost of your implementation from Exercise 4.3.2?
4.3.6 [20] <4.1, 4.2> Change your design to minimize the latency, then to minimize the cost. Compare the cost and latency of these two optimized designs.