Exercise 4.34 This exercise is designed to help you understand the discussion of the “Pipelining is easy” fallacy from Section 4.13. The fi rst four problems in this exercise refer to the following MIPS instruction:

Instruction Interpretation

a. add Rd,Rs,Rt Reg[Rd]=Reg[Rs]+Reg[Rt]

b. lw Rt,Offs(Rs) Reg[Rt]=Mem[Reg[Rs]+Offs]

4.34.1 [10] <4.13> Describe a pipelined datapath needed to support only this instruction. Your datapath should be designed with the assumption that the only instructions that will ever be executed are instances of this instruction.

4.34.2 [10] <4.13> Describe the requirements of forwarding and hazard detection units for your datapath from Exercise 4.34.1.

4.34.3 [10] <4.13> What needs to be done to support undefi ned instruction exceptions in your datapath from Exercise 4.34.1. Note that the undefi ned instruction exception should be triggered whenever the processor encounters any other kind of instruction.
The remaining two problems in this exercise also refer to this MIPS instruction:
Instruction Interpretation

a. beq Rs, Rt, Label if Reg[Rs] == Reg[Rt] PC=PC+Offs

b. and Rd, Rs, Rt Reg[Rd]=Reg[Rs]&Reg[Rt]
4.34.4 [10] <4.13> Describe how to extend your datapath from Exercise 4.34.1 so it can also support this instruction. Your extended datapath should be designed to only support instances these two instructions.
4.34.5 [10] <4.13> Repeat Exercise 4.34.2 for your extended datapath from Exercise 4.34.4.
4.34.6 [10] <4.13> Repeat Exercise 4.34.2 for your extended datapath from Exercise 4.34.4.