Exercise 4.36 This exercise is intended to help you better understand the last pitfall from Section 4.13—failure to consider pipelining in instruction set design. The fi rst four problems in this exercise refer to the following new MIPS instruction:

Instruction Interpretation

a. lwinc Rt,Offset(Rs) Reg[Rt]=Mem[Reg[Rs]+Offset]

Reg[Rs]=Reg[Rs]+4

b. addr Rt,Offset(Rs) Reg[Rt]=Mem[Reg[Rs]+Offset]+Reg[Rt]

4.36.1 [10] <4.11, 4.13> Translate this instruction into MIPS micro-operations.

4.36.2 [10] <4.11, 4.13> How would you change the fi ve-stage MIPS pipeline to add support for micro-op translation needed to support this new instruction?

4.36.3 [20] <4.13> If we want to add this instruction to the MIPS ISA, discuss the changes to the pipeline (which stages, which structures in which stage) that are needed to directly (without micro-ops) support this instruction.
4.36.4 [10] <4.13> How often do you expect this instruction can be used. Do you think that we would be justifi ed if we added this instruction to the MIPS ISA?
The remaining two problems in this exercise are about adding a new addm instruction to the ISA. In a processor to which addm has been added, these problems assume the following breakdown of clock cycles according to which instruction is completed in that cycle (or which stall is preventing an instruction from completing):
add beq lw sw addm Control Stalls Data Stalls

a. 35% 20% 20% 10% 5% 5% 5%

b. 25% 10% 25% 10% 10% 10% 10%
4.36.5 [10] <4.13> Given this breakdown of execution cycles in the processor with direct support for the addm instruction, what speed-up is achieved by replacing this instruction with a 3-instruction sequence (lw, add, and then sw)?
Assume that the addm instruction is somehow (magically) supported with a classical fi ve-stage pipeline without creating resource hazards.
4.36.6 [10] <4.13> Repeat Exercise 4.36.5, but now assume that addm was supported by adding a pipeline stage. When addm is translated, this extra stage can be removed and, as a result, half of the existing data stalls are eliminated. Note that the data stall elimination applies only to stalls that existed before addm translation, not to stalls added by the addm translation itself.