Exercise 5.5 Recall that we have two write policies and write allocation policies, their combinations can be implemented at either in L1 or L2 cache.

L1 L2

a. Write-back, write allocate Write-through, non write allocate

b. Write-back, write allocate Write-through, write allocate 5.5.1 [5] <5.2, 5.5> Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given confi guration, list the possible buffers needed between L1 and L2 caches, as well as L2 cache and memory.

5.5.2 [20] <5.2, 5.5> Describe the procedure of handling an L1 write miss, considering the component involved and the possibility of replacing a dirty block.

5.5.3 [20] <5.2, 5.5> For a multilevel exclusive cache (a block can only reside in one of the L1 and L2 caches) confi guration, describe the procedure of handling an L1 write miss, considering the component involved and the possibility of replacing a dirty block.

Consider the following program and cache behaviors.

Data reads per 1000 instructions Data writes per 1000 instructions Instruction cache miss rate Data cache miss rate Block size

(byte)

a. 200 160 0.20% 2% 8

b. 180 120 0.20% 2% 16 5.5.4 [5] <5.2, 5.5> For a write-through, write-allocate cache, what’s the minimum read and write bandwidths (measured by byte-per-cycle) needed to achieve a CPI of 2?

5.5.5 [5] <5.2, 5.5> For a write-back, write-allocate cache, assuming 30% of replaced data cache blocks are dirty, what’s the minimal read and write bandwidths needed for a CPI of 2?

5.5.6 [5] <5.2, 5.5> What are the minimal bandwidths needed to achieve the performance of CPI = 1.5?