Assuming stall-on-branch and no delay slots, what is the new clock cycle time and execution time of

Question:

Assuming stall-on-branch and no delay slots, what is the new clock cycle time and execution time of this instruction sequence if BEQ address computation is moved to the MEM stage? What is the speedup from this change? Assume that the latency of the EX stage is reduced by 20ps and the latency of the MEM stage is unchanged when branch outcome resolution is moved from EX to MEM.

The remaining problems in this exercise assume that individual pipeline stages have the following latencies: a. b. IF 200ps 150ps ID 120ps 200ps EX 150ps 200ps MEM 190ps 200ps WB 100ps 100ps