For each stage of the pipeline, determine the values of exception- related control signals from Figure 4.66 as this instruction passes through that pipeline stage.

This exercise explores how exception handling affects control unit design and processor clock cycle time. The first three problems in this exercise refer to the following MIPS instruction that triggers an exception:

Transcribed Image Text:

80000180 IF.Rush Instruction mo mory IF ID Hazard detection unit Control Shift Sign- extend ID.Rush Registers U IDVEX WB M EX Cause EPC MON *==++ EX.Flush MUN ALU EX/MEM WB Forwarding unit M Data memory MEMWB WB 4