What new signals do we need (if any) from the control unit to support this instruction?

The basic single-cycle MIPS implementation in Figure 4.2 can only implement some instructions. New instructions can be added to an existing ISA, but the decision whether or not to do that depends, among other things, on the cost and complexity such an addition introduces into the processor datapath and control. The first three problems in this exercise refer to this new instruction:

Figure 4.2

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a. b. Instruction SEQ Rd, Rs. Rt LWI Rt, Rd (Rs) Reg[Rd] Reg[Rt] = Interpretation Boolean value (0 or 1) of (Reg[Rs] Reg[Rs]) Mem[Reg[Rd]+Reg[Rs ]]