Question: We can see by the instruction encodings (Figures 4.2 and 4.3) that the rrmovq instruction is the unconditional version of a more general class of

We can see by the instruction encodings (Figures 4.2 and 4.3) that the rrmovq instruction is the unconditional version of a more general class of instructions that include the conditional moves. Show how you would modify the steps for the rrmovq instruction below to also handle the six conditional move instructions. You may find it useful to see how the implementation of the jXX instructions (Figure 4.21) handles conditional behavior.

Stage Fetch Decode Execute Memory Write back PC update cmovXX rA, rB + icode: ifun M [PC] rA:rB M[PC + 1]

Figures 4.2

Byte halt nop rrmovq rA, rB irmovq V, rB rmmovq rA, D(rB) mrmovq D(rB), rA OPq rA, rB jXX Dest cmovXX rA, rB

Figures 4.3

Operations addq 6 subq 6 1 andq 6 2 xorq 6 0 3 jmp 7 jle 7 j1 je 7 Branches 0 1 2 7 3 jne 7 jge 4 7 5 jg 7 6

Figures 4.21

Stage Fetch Decode Execute Memory Write back PC update JXX Dest icode: ifun  M[PC] valC+ Mg[PC + 1] valp  PC

Stage Fetch Decode Execute Memory Write back PC update cmovXX rA, rB + icode: ifun M [PC] rA:rB M[PC + 1] PC+2 valp valA valE - R[RA] 0+ valA R[rB] valE PC- valp

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