Modify the multicycle MIPS processor to implement one of the following instructions. See Appendix B for a definition of the instructions. Mark up a copy of Figure 7.27 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Figure 7.39 to show the changes to the controller FSM. Describe any other changes that are required. 

(a) srlv 
(b) ori 
(c) xori 
(d) jr 

CLK PCWrite Branch PCEN lorD Control PCSrc Unit ALUControl ALUSrcB, MemWrite IRWrite 3126 ALUSrcA Op Funct RegWrite CLK CLK CLK CLK CLK SrcA WE WE3 Zero CLK 2521 A. PC Instr A1 RD1 OAdr A RD B ALUOut 20 16 ALUResult 00 SrcB EN EN A2 RD2 Instr/Data 2016 Register 01 Memory A3 File 10 15:11 CLK WD 11 Data WD3 Signimm 150 Sign Extend Figure 7.27 Complete multicycle MIPS processor MemtoRec RegDst