Sketch the state transition diagram for the FSM described by the following HDL code.? SystemVerilog VHDL module

Sketch the state transition diagram for the FSM described by the following HDL code.?

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SystemVerilog VHDL module fsm2(input logic clk. reset. 11brary IEEE; use IEEE.STD_LOGIC_1164.all: input logic a. b. output logic y): logic [1:0] state, nextstate: entity fsm2 is port(clk, reset: in STD_LOGIC: in STD LOGIC: out STD LOGIC): a. b: y: parameter SO - 2'b00: parameter S1 = 2'b01: parameter S2 = 2'b10: parameter S3 = 2'b11: end: archítecture synth of fsm2 is type statetype is (S0. S1. S2. $3): signal state, nextstate: statetype: begin process (clk, reset) begin 1f reset then state (= S0: elsif rising edge(clk) then always_ff @(posedge clk. posedge reset) if (reset) state <= S0: else state (= nextstate: always_comb case (state) state <= nextstate: So: If (a ^ b) nextstate = Si: else S1: if (a & b) nextstate = S2: end 1f: nextstate = $0: end process: process(all) begin else nextstate = S0: case state is $2: if (a | b) nextstate = S3: when S0 => if (a xor b) then nextstate (= S1: nextstate = S0: else S3: if (a | b) nextstate = S3: else else nextstate <= $0; end if: nextstate = SO: endcase when S1 => 1f (a and b) then assign y = (state== $1) | (state== $2): nextstate <- s2: else nextstate <= $0; end if: endmodule when S2 => 1f (a or b) then nextstate <= S3: else nextstate <= S0: end if: when S3 => 1f (a or b) then nextstate <= $3: else nextstate <= S0: end if: end case: end process: y <= '1' when ((state = S1) or (state= S2)) else '0': end: