Question: Write and verify the VHDL that implements your state machine from Exercise 14.3. Data in Exercise 14.3. Cycle 0 1 2 3 4 5 6
Write and verify the VHDL that implements your state machine from Exercise 14.3.
Data in Exercise 14.3.
Cycle 0 1 2 3 4 5 6 7 8 9 State 00 00 01 11 01 11 10 11 10 00 In 0 1 1 0 1 1 0 1 1 Out 0 0 0 0 0 0 0 0 1 0
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