In the adder and subtractor circuits discussed in this chapter, we gave no consideration to the possibility of overflow. Overflow occurs when the two numbers being added or subtracted produce a result that contains more bits than the capacity of the accumulator. For example, using four-bit registers, including a sign bit, numbers ranging from +7 to –8 (in 2’s complement) can be stored. Therefore, if the result of an addition or subtraction exceeds +7 or –8, we would say that an overflow has occurred. When an overflow occurs, the results are useless because they cannot be stored correctly in the accumulator register. To illustrate, add +5 101012 and +4 101002, which results in 1001. This 1001 would be interpreted incorrectly as a negative number because there is a 1 in the sign-bit position.

In computers and calculators, there are usually circuits that are used to detect an overflow condition. There are several ways to do this. One method that can be used for the adder that operates in the 2’s-complement system works as follows:

1. Examine the sign bits of the two numbers being added.

2. Examine the sign bit of the result.

3. Overflow occurs whenever the numbers being added are both positive and the sign bit of the result is 1 or when the numbers are both negative and the sign bit of the result is 0.

This method can be verified by trying several examples. Try the following cases: 112 5 + 4; 122 – 4 + 1–62; (3) 3 + 2. Cases 1 and 2 will produce an overflow, and case 3 will not. Thus, by examining the sign bits, one can design a logic circuit that will produce a 1 output whenever the overflow condition occurs. Design this overflow circuit for the adder of Figure 6-10.

Figure 6-10

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LOAD> C4 CLEAR> TRANSFER> CLKD FA D >CLK B₂ A₂ CLR CLEAR LOAD TRANSFER I I 4 1 T CLK D DCLK 12 FA CLR D B₂ A₂ T 1 13 S₁ CLK 1₂ FA D >CLK CLR (h) D B₂ 100 A₁ Accumulator outputs (a) 1 1 5 Sor CLK D FA D >CLK CLR Bo Ao B register -Co 4-bit adder A register