Exercise 8.16 (Technology Mapping and Verification). Draw both the graph that describes the behavior of the sequential circuit and the circuit structure calculated in Exercises 8.12 . . . 8.15. Verify whether the behavior of the designed structure is covered by the allowed behavior defined in Exercise 8.11. Compare both the required numbers of gates and the depth of the designed structure with the given sequential circuit of Fig. 8.2. Practical tasks:

1 Load theTVL systeme8305.sdt of Exercise 8.15. This TVL system includes the system function F(x, s, sf , y) of the given non-deterministic finite-state machine as object number 1 and the respective system function F(x, s, sf , y) of the designed sequential circuit as object number 9.

2 Show the global lists of phases of both the given non-deterministic finitestate machine of object number 1 and the designed deterministic finitestate machine of object number 9.

3 Draw the graph of the designed finite-state machine and describe the visualized behavior in comparison to the graph of Fig. 8.7.

4 Draw the structure of the sequential circuit calculated by solving equations with regard to variables in Exercises 8.12. . . 8.15. As in Fig. 8.2 the number of inputs of the gates is restricted to three.

5 Verify whether the behavior of the structure of the sequential circuit is covered by the allowed behavior defined in Exercise 8.11.

6 Compare both the required numbers of gates and the depth of the designed circuit structure with the given sequential circuit of Fig. 8.2.