Assume a computer has L1 and L2 caches, as discussed in Section 5.6.3. The cache blocks consist of 8 words. Assume that the hit rate is the same for both caches and that it is equal to 0.95 for instructions and 0.90 for data. Assume also that the times needed to access an 8-word block in these caches are C = 1 cycle and C = 10 cycles.

(a) What is the average access time experienced by the processor if the main memory uses interleaving? Assume that the memory access parameters are as described in Section 5.6.1.

(b) What is the average access time if the main memory is not interleaved?

(c) What is the improvement obtained with interleaving?