Instruction 12 in Figure 8.6 is delayed because it depends on the results of I. By occupying the Decode stage, instruction I2 blocks I3, which, in turn, blocks I4. Assuming that I3 and 14 do not depend on either I, or I2 and that the register file allows two Write steps to proceed in parallel, how would you use additional storage buffers to make it possible for 13 and 14 to proceed earlier than in Figure 8.6? Redraw the figure, showing the new order of steps.

LO1