3. Define the following points in Figure 11.10: (1) A is the output of the top master AND gate.

(2) B is the output of the bottom master AND gate. (3) C is the output of the inverter. (4) D is the output of the top slave AND gate. (5) E is the output of the bottom slave AND gate.

Suppose SR = 10 and Q = 0 before the arrival of a clock pulse. Construct a table that shows the values of A, B, C, D, E, R2, S2, Q, and Q during each of the following intervals of Figure 11.11, assuming zero gate delay:

*

(a) before t1

*

(b) between t1 and t2

(c) between t2 and t3

(d) between t3 and t4

(e) after t4