What is the minimum number of gates required to construct a 6 x 64 decoder? Assume that 6-input logic gates are feasible. What is the worst case propagation delay for the decoder in units of gate delays? How does this compare to the number of gates needed to build a 6-bit ripple-carry adder, an adder that accepts inputs represented using 6 bits, and to the worst case propagation delay adder? What is the ratio of speed decoder to adder?