You have a 64-bit machine and you bought 4GB of physical memory. Pages are 64KB.

(a) How many virtual pages do you have per process?

(b) How many physical pages do you have?

(c) In the translation from a virtual address to a physical address, how many bits of VPN are you mapping to how many bits of PPN (assuming you have just enough bits in the physical address for the amount of physical RAM present)?

(d) How big does a page table entry (PTE) need to be to hold just a single PPN?

(e) How many PTEs fit on a page, assuming PTEs are the size computed in part (d)?

(f) How many pointers fit on a page?

(g) How big would a flat page table be for a single process, assuming PTEs are the size computed in part (d)?

(h) What are the virtual page offset bits for virtual address 35012? What are the physical page offset bits for virtual address 35012 after it has been translated?

(i) Does a TLB miss always lead to a page fault? Why or why not?