0 Large and Fast: Exploiting Memory Hierarchy Assume the following address sequence generated by the microprocessor: Time 1 2 3 4 Access 1000 1101 1011 0010 1011 1111 1000 1100 1001 1100 Tag 10001 Set Index 1 Byte Offset 01 The cache uses 4 bytes per block. Assume a 2-way set-associative cache design that uses the LRU algorithm (with a cache that can hold a total of 4 blocks). Assume that the cache is initially empty. Detennine the Tag. Set Index, and Byte Offset fields by filling in the table above in binary. b) Using the setup in Problem 5 a). In the figure below, clearly mark for each access the Tag, Least Recently Used (LRU) (1 if LRU), and Hit/Miss (1 if Hit) information for each access. Initial Access o Block 0 Block 1 Block 0 Block 1 Tag LRU Hit Tag LRU Hit Tag LRU Hit Tag LRU Hit Seto Seto Setl Setl 10001 0 0 Access 1 Access 2 Block 0 LRU Hit Tag Block 1 LRU Hit Block 0 LRU Block 1 LRU Hit Tag Tag Hit Tag Seto Setl Seto Setl Access 3 Access 4 Block 0 LRU Hit Tag Block 1 LRU Hit Block 0 LRU Hit Tag Block 1 LRU Hit Tag Tag Seto Set 1 Seto Setl c) For a direct-mapped cache design with a 32-bit address and the following address subdivision. Tag Index Offset 31-10 9-5 4-0 1. What is the total number of bits required for this cache implementation? 11 If the overhead bits are all cache bits except data bits. What is the overhead ratio? d) Given an 8-way set associative cache that has 16 blocks and 32 bytes per block. Assume a 32-bit address. Calculate the following: How many bits are used for the byte offset? ii. How many bits are used for the set (index) field? 111 How many bits are used for the tag? 5