$10.$Assure a processor has $3$ levels of caches. Suppose that the tirne required

to access the Ll $($primary$)$ cache on a hit is $1$ cycle, the local Ll cache

hit ratio is $0\mathrm{.}90,$ the to access the L$2($secondary$)$ cache on a hit

is $5$ cycles, the local L$2$ cache

miss ratio is $0\mathrm{.}25,$ the tire to access

the L$3$ cache on a hit is $10$ cycles, the local L$3$ cache hit ratio is

$0\mathrm{.}50,$ and the L$3$ cache miss penalty to access main $$mory is $100$ cycles.

Give the average access time. Also give the average access

if this processor did not have an L$2$ and L$3$ cache.