$(10$pts$)$ Here is a series of address references given as word addresses: $1,20,9,4,17,9,10,4,9,20,25,13,12.$ Assume a direct$-$mapped cache with $4$ one$-$word blocks that initially empty, label each memory reference in the list as a hit or a miss and show the final cache contents in the table below. Assume memory address is $6-$bit long $($given in parenthesis$).$ What is the miss rate?

$\backslash$table$[[$Reference$,$Hit or miss$],[1(000001),],[20(010100),],[9(001001),],[4(000100),],[17(010001),],[9(001001),],[10(001010),],[4(000100),],[9(001001),],[20(010100),],[25(011001),],[13(001101),],[12(001100),]]$

$\backslash$table$[[\backslash$table$[[$Cache$],[$Block$]],\backslash$table$[[$Valid$],[$bit$]],$Tag,Data$],[0,,,],[1,,,],[2,,,],[3,,,]]$

Miss rate $=$