$1.[1$ Pts$]$ Provide all Verilog design files and constraint files of the lab experiments.

$2.[3$ Pts$]$ Update Exp$2$ to implement the full architecture shown in figure $2,$ after adding data$1.$ Note

that data$1$ should now be added to the ROM word.

$3.[2$ Pts$]$ Write a microprogram to do the following operation: w $=($x $|$ y$)+($x & z$)-138$ where x $=124,$

y $=28,$ z $=199.$ You should divide this operation to micro$-$operations and fill in a table for the

instruction word for each micro$-$operation, same as you did in Exp$1.$

$4.[4$ Pts$]$ Write a testbench to simulate the datapath of Q$2,$ using the microprogram of Q$3.$ Attach a

screenshot of the simulation waveform output on Vivado.