1. [10 points] Suppose each stage of the instruction takes the following times: IF (Instruction Fetch) = 7 ns, ID (Instruction Decode) = 8 ns, EX (Execution) = 13 ns, MEM (Memory Access) = 10 ns, WB (Write Back) = 8 ns Assume that there is 1 ns overhead to read and 1 ns overhead to write to pipeline register in the pipelined implementation. Ignore the overhead due to additional temporary registers and multiplexors used in the multiple cycle implementation. i. What is the cycle time for a single cycle, multiple cycle, and pipelined processor? ii. How long will each take to implement 4 add instructions assuming no hazards occur? Which implementation has the longest execution time? Why?