1. (15 points) Consider the following CPU parameters: CPU has a 1 ns clock cycle time. The Li cache (both I$ and D$) hit time = 1 cycle. The miss penalty - 100 cycles for both caches. I$ miss rate = 4%, D$ miss rate = 10%. Load and store are 30% of instructions Answer the following questions in the table below, show your derivations and work a. (3 points) Compute the stall cycles per instruction due to the I$ b. (3 points) Compute the stall cycles per instruction due to the D$ C. (3 points) Compute the real CPI, assume the ideal CPI (with a perfect cache) is 1 d. (3 points) What fraction of its time does the CPU spend waiting for memory? e. (3 points) What is the average memory access time (AMAT)? (1 point for correct result, 2 points for correct derivation)