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From a hardware perspective, what is the best way to decrease conflict misses? Increase cache size Increase cache associativity Increase block size Decrease miss penalty Consecutive instructions that are infrequently executed display: Spatial Locality Temporal Locality Both Spatial and Temporal Locality Neither Spatial nor Temporal Locality If the system slows down dramatically when many programs are in use and the disk usage spikes, what is the best diagnosis of this problem? Compulsory cache misses > change the processor Slow disk subsystem -> replace the disk controller Virtual memory thrashing -> add more system memory Network latency -> add a faster network card The class lecture notes mentions a possible way to achieve better scalability than predicted by Amdahl's law. How? Using an infinite number of processors Increasing the processor speed Improved cache hit rates due to smaller data set sizes Misreporting the system benchmark numbers Which is not true of fine-grained hardware multithreading Threads are switched after every cycle Instruction execution of multiple threads are interleaved If one thread stalls, others are executed Switches only occur after long stalls Multi-core and multi-threaded hardware are mutually exclusive True False Multiprocessing attempts to achieve performance through: Parallelism Redundancy Hierarchy of memory Moore's Law Parallel software must be run on parallel hardware True False On multithreaded/multi-core hardware, what is affinity? A set preference of which core/thread your code will run on A preference on which threads will run simultaneously A preference for which threading libraries are used None of these pthread_setaffinity_np() can improve cache performance by setting the affinity for a specific program thread. True False Transmission latency is the amount of time it takes for data to move from the transmitter to the receiver? True False Which of the following threading techniques is most likely to have "cache coloring" issues? Fine-grained multithreading Course-grained multithreading Thread-per core, with affinity set All equally likely If a half of a piece of serial code can be parallelized, what is the maximum amount of speedup that can be expected? 2x0.5x Infinite Not enough information Network latency is the total amount of data that can be transmitted over one second? True False Which of the following is not a software challenge when writing code for a SMP system False sharing (same cache block used by different cores) Synchronizing shared variables using locks Potential race conditions Increasing the processor clock speed
