1. [3 marks] Equal-lengthed Stages Consider the design of a processor, with a max instruction length of 900 ps. The propagation delay to

load a register is 25 ps.

1. (a) [1 mark] What is the minimum clock cycle time, the instruction latency and CPU throughput using serial execution?

2. (b) [1 mark] What is the minimum clock cycle time, the instruction latency and CPU throughput using a pipelined execution with 12 equal stages?

3. (c) [1 mark] Consider a design which used n equal stages. What is the minimum clock cycle time, the instruction latency and CPU throughput expressed as a function of n? (You may wish to check that your generalization agrees with your results from parts (a) and (b), i.e., by substituting n = 1, 12.)

Reducing Cycle Times Strategy: Divide each assembly instruction into stages m ohe Five Stages: 1. fetch (F) 2. decode (D) 3. calculate (C) 4. memory (M) 5. write back (W) -Z/>H-| | in.ney DoQgwe, on each have to do al hme The Five Stages e fetch (F) Some upgrades to the ISA: e machine is 2-operand o load next instruction e decode (D) e opcode is 8-bit o prepare operation (function select o load all operands save copy of the current instruction calculate (C) save intermediate calculations o compute resu st67 memory (M) o access extemal memory (read/write) write back (W) Reducing Cycle Times Strategy: Divide each assembly instruction into stages m ohe Five Stages: 1. fetch (F) 2. decode (D) 3. calculate (C) 4. memory (M) 5. write back (W) -Z/>H-| | in.ney DoQgwe, on each have to do al hme The Five Stages e fetch (F) Some upgrades to the ISA: e machine is 2-operand o load next instruction e decode (D) e opcode is 8-bit o prepare operation (function select o load all operands save copy of the current instruction calculate (C) save intermediate calculations o compute resu st67 memory (M) o access extemal memory (read/write) write back (W)