$18$

$1$ point

Consider the $5-$stage pipeline with Fetch, Decode, Execute, Memory Access, Write Back. A forwarding$/$bypassing connection is available.

Consider the following instruction sequence:

$i1$: LDUR $x,[x,$#$]$

$i2$: ADD $x1,x,x$

can avoid stalls using only forwarding

can execute without stalling or forwarding

must stall