1. Analyze the following circuit. Assume clock skew is 200 ps a. b. C. Label the critical path of the circuit. What is the maximum frequency of the circuit? Does the circuit have any hold time violations? If so, correct them using NOT gates and having a minimal impact on the clock frequency DFF-3 DFF-1 D a CLK DFF-4 CLK DFF-2 D a 0 D Q CLK CLK GateTcd NOT AND 250 ps400 ps OR XOR MUX 300 ps 700 ps Tpd 100 ps 150 ps 250 ps 350 ps 400 ps 600 ps Tsetup Thold Tccq Tpcq 250 ps 600 ps 400 ps 1200 ps 1. Analyze the following circuit. Assume clock skew is 200 ps a. b. C. Label the critical path of the circuit. What is the maximum frequency of the circuit? Does the circuit have any hold time violations? If so, correct them using NOT gates and having a minimal impact on the clock frequency DFF-3 DFF-1 D a CLK DFF-4 CLK DFF-2 D a 0 D Q CLK CLK GateTcd NOT AND 250 ps400 ps OR XOR MUX 300 ps 700 ps Tpd 100 ps 150 ps 250 ps 350 ps 400 ps 600 ps Tsetup Thold Tccq Tpcq 250 ps 600 ps 400 ps 1200 ps