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1) assume that a load word instruction on a single cycle architecture takes 200ps to finish on a single cycle architecture. Allowing for 50 ps
1) assume that a load word instruction on a single cycle architecture takes 200ps to finish on a single cycle architecture. Allowing for 50 ps overhead, what is the maximum clock frequency this architecture can be operated at?
2) describe some shortcomings of this architecture. How can you improve?
i need number 2
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