$1.$Based on how binary information is entered or shifted out, shift registers areclassified into $\_\_\_\_\_\_\_$ categories.a : $2$ b : $3$ c : $4$ d : $52.$How can parallel data be taken out of a shift register simultaneously?a : Use the Q output of the first FF b : Use the Q output of the last FFc : Tie all of the Q outputs together d : Use the Q output of each FF$3.$The group of bits $11001$ is serially shifted $($right$-$most bit first$)$ into a $5-$bit paralleloutput shift register with an initial state $01110.$ After three clock pulses, the registercontains $\_\_\_\_\_\_\_\_$a : $01110$ b : $00001$ c : $00101$ d : $001014.$The full form of SIPO is $\_\_\_\_\_\_\_\_\_\_\_$a : Serial$-$in Parallel$-$out b : Parallel$-$in Serial$-$outc : Serial$-$in Serial$-$out d : Serial$-$In Peripheral$-$Out$5.$A shift register that will accept a parallel input or a bidirectional serial load andinternal shift features is called as$?$a : Tristate b : End around c : Universa l d : Conversion$6.$ The register is a type of$\_\_\_\_\_\_\_\_\_\_\_$a$)$ Sequential circuit b$)$ Combinational circuitc$)$ CPU d$)$ Latches$7.$ The main difference between a register and a counter is$\_\_\_\_\_\_\_\_\_\_\_$a$)$ A register has no specific sequence of statesb$)$ A counter has no specific sequence of statesc$)$ A register has capability to store one bit of information but counter has n$-$bitd$)$ A register counts data$\mathrm{.}8.$ In D register, D stands for$\_\_\_\_\_\_\_\_\_\_\_$a$)$ Delayb$)$ Decrement$223$CCE$-$ Digital Logic DesignLab Manual KKU$-$CS$-$CE$$ C o m p u t e r E n g i n e e r i n g D e p t $.$ H a r u n B a n g a l i Page $31$c$)$ Datad$)$ Decay$9.$Registers capable of shifting in one direction is$\_\_\_\_\_\_\_\_\_\_\_$a$)$ Universal shift registerb$)$ Unidirectional shift registerc$)$ Unipolar shift registerd$)$ Unique shift register$10.$ A register that is used to store binary information is called$\_\_\_\_\_\_\_\_\_\_\_$a$)$ Data registerb$)$ Binary registerc$)$ Shift registerd$)$ D Register