1. Calculate the following quantities for a differential pair with resistive CMFB. The input pair is...
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1. Calculate the following quantities for a differential pair with resistive CMFB. The input pair is biased at a common mode voltage of 0.6 V. The tail transistor M5 is designed to operate in the saturation region as a current source, and its drain-source voltage is 0.5 V. Use the following data to answer questions 1.1 - 1.4. Neglect the body effect and the channel length modulation effect during the la calculation. Assuming none of these transistors works in the cut-off or subthreshold region. item Size of M, M Size of M3, M4 UpCax of M, M Hn Cox of M3, M4 Van and Vap RD VDD Vin, CM Vs p and An Vin10- Vout-o Ms 10 M www RD V Value 24 um / 1um 12 um/ lum 125 UA/V 250 uA/V Ms Iss 0.5 V 2 1.8 V 0.6 V 1.3 V 0.04 V-1 M RD VDD M 102 -o Vin2 - Vout+ Figure 1. Circuits to characterize for exercise 1 1.1 (2 points) Check the operation regions of M ~ M4. If they work in the saturation region, please calculate its DM and CM gain; if not, please explain your findings. 1.2 (0.5 point) Assuming the drain voltage Vs of the current source M, is unknown, while the gate voltage Vi can be tuned, what is the maximum allowable input CM level? Write your answer as an expression. 1.3 (0.5 point) How does the output voltage change if the input CM level is 100 mV higher than 1.1V? 1.4 (1 point) Derive the equation between (ID1 - ID2) and (Vint - Vin2). How is the tail current shared between the two sides if Vint - Vin2= 25 mV? 1. Calculate the following quantities for a differential pair with resistive CMFB. The input pair is biased at a common mode voltage of 0.6 V. The tail transistor M5 is designed to operate in the saturation region as a current source, and its drain-source voltage is 0.5 V. Use the following data to answer questions 1.1 - 1.4. Neglect the body effect and the channel length modulation effect during the la calculation. Assuming none of these transistors works in the cut-off or subthreshold region. item Size of M, M Size of M3, M4 UpCax of M, M Hn Cox of M3, M4 Van and Vap RD VDD Vin, CM Vs p and An Vin10- Vout-o Ms 10 M www RD V Value 24 um / 1um 12 um/ lum 125 UA/V 250 uA/V Ms Iss 0.5 V 2 1.8 V 0.6 V 1.3 V 0.04 V-1 M RD VDD M 102 -o Vin2 - Vout+ Figure 1. Circuits to characterize for exercise 1 1.1 (2 points) Check the operation regions of M ~ M4. If they work in the saturation region, please calculate its DM and CM gain; if not, please explain your findings. 1.2 (0.5 point) Assuming the drain voltage Vs of the current source M, is unknown, while the gate voltage Vi can be tuned, what is the maximum allowable input CM level? Write your answer as an expression. 1.3 (0.5 point) How does the output voltage change if the input CM level is 100 mV higher than 1.1V? 1.4 (1 point) Derive the equation between (ID1 - ID2) and (Vint - Vin2). How is the tail current shared between the two sides if Vint - Vin2= 25 mV?
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Solutions Step 1 11 Assuming none of these transistors works in the cutoff or subthreshold region M1 and M2 are in the saturation region because their Vds 05 V is greater than VgsVth M3 and M4 are in ... View the full answer
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