1. Consider a system built on a 50 MHz TM4C123 with the main loop and an interrupt which occurs at a 10 kHz frequency. Assume the ISR takes 15 us to execute and there is a total of 1 us of response and return time overhead.

a. What percentage of the processors time is spent in interrupt response and return overhead?

b. what percentage of the processors time is left for the main loop to execute?

c. If the main loop requires 37 ms of computation to execute one iteration, what is the minimum main loop update rate (in Hz)?