1. Consider an 8MB direct-mapped data cache that uses a 32-bit address and 32 bytes per block. As usual assume 32-bit words. (a) How many bits are used for the block offset? For word offset? (b) How many bits are used for the index? (c) How many bits are used for the tag? (d) Provide the design of this cache similar as on Slides H36 or H37, including gates, multiplexers and comparators where needed. (e) Assuming that CPU generates address 0xABCDE678 and it is a hit, - what is the cache entry accessed? - indicate as much as possible of contents for that entry.