1. Consider the assembly snippet shown. Operation Clock cycle multiply 12 load add divid 24 32 (R2) 44 (R3) ; L.D takes 1 cycle F6 F2 2 L.D 3 MUL.D FO 4 SUB.DF8 5 DIV.D F10, FO, 6 ADD.D F6 F4 6 cycles F6 2 cycles F6 12 cycle F2; 2 cycles F 2 F2 F 8 It is assumed that after the first load instruction, the memory is busy and not available to the processor at least at the 6th cycle. At the 6th cycle, the tables are shown ([Rx] means the content of register Rx) RSidBusy 100 102 80 23 no yes yesMUL.D yesSUB.D yesDIV.D yes | ADD.D R3] 44 [R3] [F4] [F6] [F6] L.D 102 102 80 23 0 0 0 0 102 52 F31 F2 102 Field FO F4 F6 F8 F10 F12 80 52 23 a. At the 20th cycle, the second load just placed the data on the CDB. Therefore, at 21st cycle, reservation station 102 is released and instructions that require the second load result get the result from the CDB and start execution of their respective operations. Show the table at the 21th clock cycle b. The SUB.D executes the subtraction during cycle 21 and 22, places the result on CDB at cycle 23. Show the table at the 24th clock cycle. c. Show the table the 27th clock cycle d. At what cycle, instruction MULT.D places result on CDB? e. If reservation station for instruction MULT.D is released at cycle 24, at what cycle instruction DIV.D finishes execution? f. At cycle 100, show the tables 1. Consider the assembly snippet shown. Operation Clock cycle multiply 12 load add divid 24 32 (R2) 44 (R3) ; L.D takes 1 cycle F6 F2 2 L.D 3 MUL.D FO 4 SUB.DF8 5 DIV.D F10, FO, 6 ADD.D F6 F4 6 cycles F6 2 cycles F6 12 cycle F2; 2 cycles F 2 F2 F 8 It is assumed that after the first load instruction, the memory is busy and not available to the processor at least at the 6th cycle. At the 6th cycle, the tables are shown ([Rx] means the content of register Rx) RSidBusy 100 102 80 23 no yes yesMUL.D yesSUB.D yesDIV.D yes | ADD.D R3] 44 [R3] [F4] [F6] [F6] L.D 102 102 80 23 0 0 0 0 102 52 F31 F2 102 Field FO F4 F6 F8 F10 F12 80 52 23 a. At the 20th cycle, the second load just placed the data on the CDB. Therefore, at 21st cycle, reservation station 102 is released and instructions that require the second load result get the result from the CDB and start execution of their respective operations. Show the table at the 21th clock cycle b. The SUB.D executes the subtraction during cycle 21 and 22, places the result on CDB at cycle 23. Show the table at the 24th clock cycle. c. Show the table the 27th clock cycle d. At what cycle, instruction MULT.D places result on CDB? e. If reservation station for instruction MULT.D is released at cycle 24, at what cycle instruction DIV.D finishes execution? f. At cycle 100, show the tables
