1. Consider the code segment in RISC-V which is similar to LEGV8 fld f, 0(x0 load fo from address 0+x0 fld f2, 0(x2) load f2 from address 0+x2 fmult f2, f2, fo 2 f2*fo fsd f2, 0(x2) store x2 at address 0+x2 addwi x2, x2, 8x2 +8 subwi x4, x3, x2 ;x4 x3-x2 bne x4, x0, loop branch to loop if x4!-0 Loop: Assume the initial value of x3 is x2+64. Assume x0-0 and x2-16, and the memory contains: MO M8] M26 M24] M32] M40 MI48 M56) M64 M72] M80] |M88] 4.0 1.0 7.0 9.0 5.0 3.0 1.0 2.0 5.0 8.0 7.0 3.0 0 8 16 24 32 40 48 56 64 7280 The cache size is 64 bytes and the bock size is 16 bytes. Make a table similar with Example 5 in Lecture slides a) Display the content of memory, cache hit or miss status, and the content of cache as the loop b) Repeat Part (a) assuming cache is a 2-way set associative, with FIFO replacement policy, and executes, assuming the cache is direct mapped, with write through and no write allocate. write back, and write allocate. 1. Consider the code segment in RISC-V which is similar to LEGV8 fld f, 0(x0 load fo from address 0+x0 fld f2, 0(x2) load f2 from address 0+x2 fmult f2, f2, fo 2 f2*fo fsd f2, 0(x2) store x2 at address 0+x2 addwi x2, x2, 8x2 +8 subwi x4, x3, x2 ;x4 x3-x2 bne x4, x0, loop branch to loop if x4!-0 Loop: Assume the initial value of x3 is x2+64. Assume x0-0 and x2-16, and the memory contains: MO M8] M26 M24] M32] M40 MI48 M56) M64 M72] M80] |M88] 4.0 1.0 7.0 9.0 5.0 3.0 1.0 2.0 5.0 8.0 7.0 3.0 0 8 16 24 32 40 48 56 64 7280 The cache size is 64 bytes and the bock size is 16 bytes. Make a table similar with Example 5 in Lecture slides a) Display the content of memory, cache hit or miss status, and the content of cache as the loop b) Repeat Part (a) assuming cache is a 2-way set associative, with FIFO replacement policy, and executes, assuming the cache is direct mapped, with write through and no write allocate. write back, and write allocate