1. Draw an equivalent SR latch (Fig. B.8.1) using AND gates instead of OR gates.

2. How many logic gates are in a

a) D-latch

b) Flip-flop

c) 32-bit register

d) 16-register file (32-bit registers) (Assume that a 4-16 decoder has 64 gates and a 16-way mux has 32 gates per bit.)

Figure B.8.1 SR Latch 3. Given these S and R inputs for an SR-latch over 7 cycles, indicate where state changes will occur, by writing 'Y' in the last row. Assume that Q is initially O. State change? (Y/N)