1. Estimate the resistance per mm of a minimum pitch Cu wire for each layer in the Intel 45 nm process described in Tablel. Assume a 10 nm high-resistance barrier layer and negligible dishing. (nm) s (nm) pitch (nm) 7 um 13 um 30.5 m Layer M9 MS MZ M6 MS M4 M3 M2 M1 720 504 324 252 216 144 144 144 Table 1 w Com) 17.5 m 400 280 180 140 120 80 80 410 280 180 140 120 80 80 80 810 560 360 280 240 160 160 160