1. Given the xyzzy $rt, $rs instruction as defined above, and assuming that a memory load request takes 2 clock cycles to complete (after MEMread has been issued), how many clock cycles would it take to execute each xyzzy instruction? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here.

2. Given this processor hardware design, suppose that the following control state is the limiting factor in determining the maximum clock speed. Given that the propagation delay associated with Zin is 1ns, CONST(1) is 2ns, REGin is 4ns, SELrd is 8ns, and ALUadd is 16ns, what is the period (in nanoseconds) of the fastest allowable clock? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here:

ALUadd, CONST(1), Zin, SELrd, REGin