1. Implement the serial adder circuit as a module in Verilog. Use only gate-level modeling.

2. Create a test module that uses the serial adder module to add 16-bit two's complement integers. Run it with at least 8 test sequences that add:

the largest integer to itself

the largest integer to 1

the largest integer to 0

the largest integer to -1

the smallest integer to 1

the smallest integer to 0

the smallest integer to -1

the smallest integer to the largest integer

x Full adder C 0 ClkClock FIGURE P5.7 x Full adder C 0 ClkClock FIGURE P5.7